intTypePromotion=1
zunia.vn Tuyển sinh 2024 dành cho Gen-Z zunia.vn zunia.vn
ADSENSE

Bài giảng Hệ điều hành nâng cao - Chapter 13: I/O Systems

Chia sẻ: Xaydung K23 | Ngày: | Loại File: PPTX | Số trang:42

153
lượt xem
8
download
 
  Download Vui lòng tải xuống để xem tài liệu đầy đủ

Bài giảng Hệ điều hành nâng cao - Chapter 13: I/O systems trình bày về I/O hardware, application I/O interface, kernel I/O subsystem, transforming I/O requests to hardware operations, STREAMS, performance.

Chủ đề:
Lưu

Nội dung Text: Bài giảng Hệ điều hành nâng cao - Chapter 13: I/O Systems

  1. Chapter 13: I/O Systems Operating System Concepts – 8th8th Edition Operating System Concepts – Edition 13.1 Silberschatz, Galvin and Gagne ©2009
  2. Chapter 13: I/O Systems s I/O Hardware s Application I/O Interface s Kernel I/O Subsystem s Transforming I/O Requests to Hardware Operations s STREAMS s Performance Operating System Concepts – 8th Edition 13.2 Silberschatz, Galvin and Gagne ©2009
  3. Objectives s Explore the structure of an operating system’s I/O subsystem s Discuss the principles of I/O hardware and its complexity s Provide details of the performance aspects of I/O hardware and software Operating System Concepts – 8th Edition 13.3 Silberschatz, Galvin and Gagne ©2009
  4. Overview s I/O management is a major component of operating system design and operation q Important aspect of computer operation q I/O devices vary greatly q Various methods to control them q Performance management q New types of devices frequent s Ports, busses, device controllers connect to various devices s Device drivers encapsulate device details q Present uniform device-access interface to I/O subsystem Operating System Concepts – 8th Edition 13.4 Silberschatz, Galvin and Gagne ©2009
  5. I/O Hardware s Incredible variety of I/O devices q Storage q Transmission q Human-interface s Common concepts – signals from I/O devices interface with computer q Port – connection point for device q Bus - daisy chain or shared direct access q Controller (host adapter) – electronics that operate port, bus, device 4 Sometimes integrated 4 Sometimes separate circuit board (host adapter) 4 Contains processor, microcode, private memory, bus controller, etc – Some talk to per-device controller with bus controller, microcode, memory, etc Operating System Concepts – 8th Edition 13.5 Silberschatz, Galvin and Gagne ©2009
  6. A Typical PC Bus Structure Operating System Concepts – 8th Edition 13.6 Silberschatz, Galvin and Gagne ©2009
  7. I/O Hardware (Cont.) s I/O instructions control devices s Devices usually have registers where device driver places commands, addresses, and data to write, or read data from registers after command execution q Data-in register, data-out register, status register, control register q Typically 1-4 bytes, or FIFO buffer s Devices have addresses, used by q Direct I/O instructions q Memory-mapped I/O 4 Device data and command registers mapped to processor address space 4 Especially for large address spaces (graphics) Operating System Concepts – 8th Edition 13.7 Silberschatz, Galvin and Gagne ©2009
  8. Device I/O Port Locations on PCs (partial) Operating System Concepts – 8th Edition 13.8 Silberschatz, Galvin and Gagne ©2009
  9. Polling s For each byte of I/O 1. Read busy bit from status register until 0 2. Host sets read or write bit and if write copies data into data-out register 3. Host sets command-ready bit 4. Controller sets busy bit, executes transfer 5. Controller clears busy bit, error bit, command-ready bit when transfer done s Step 1 is busy-wait cycle to wait for I/O from device q Reasonable if device is fast q But inefficient if device slow q CPU switches to other tasks? 4 But if miss a cycle data overwritten / lost Operating System Concepts – 8th Edition 13.9 Silberschatz, Galvin and Gagne ©2009
  10. Interrupts s Polling can happen in 3 instruction cycles q Read status, logical-and to extract status bit, branch if not zero q How to be more efficient if non-zero infrequently? s CPU Interrupt-request line triggered by I/O device q Checked by processor after each instruction s Interrupt handler receives interrupts q Maskable to ignore or delay some interrupts s Interrupt vector to dispatch interrupt to correct handler q Context switch at start and end q Based on priority q Some nonmaskable q Interrupt chaining if more than one device at same interrupt number Operating System Concepts – 8th Edition 13.10 Silberschatz, Galvin and Gagne ©2009
  11. Interrupt-Driven I/O Cycle Operating System Concepts – 8th Edition 13.11 Silberschatz, Galvin and Gagne ©2009
  12. Intel Pentium Processor Event-Vector Table Operating System Concepts – 8th Edition 13.12 Silberschatz, Galvin and Gagne ©2009
  13. Interrupts (Cont.) s Interrupt mechanism also used for exceptions q Terminate process, crash system due to hardware error s Page fault executes when memory access error s System call executes via trap to trigger kernel to execute request s Multi-CPU systems can process interrupts concurrently q If operating system designed to handle it s Used for time-sensitive processing, frequent, must be fast Operating System Concepts – 8th Edition 13.13 Silberschatz, Galvin and Gagne ©2009
  14. Direct Memory Access s Used to avoid programmed I/O (one byte at a time) for large data movement s Requires DMA controller s Bypasses CPU to transfer data directly between I/O device and memory s OS writes DMA command block into memory q Source and destination addresses q Read or write mode q Count of bytes q Writes location of command block to DMA controller q Bus mastering of DMA controller – grabs bus from CPU q When done, interrupts to signal completion Operating System Concepts – 8th Edition 13.14 Silberschatz, Galvin and Gagne ©2009
  15. Six Step Process to Perform DMA Transfer Operating System Concepts – 8th Edition 13.15 Silberschatz, Galvin and Gagne ©2009
  16. Application I/O Interface s I/O system calls encapsulate device behaviors in generic classes s Device-driver layer hides differences among I/O controllers from kernel s New devices talking already-implemented protocols need no extra work s Each OS has its own I/O subsystem structures and device driver frameworks s Devices vary in many dimensions q Character-stream or block q Sequential or random-access q Synchronous or asynchronous (or both) q Sharable or dedicated q Speed of operation q read-write, read only, or write only Operating System Concepts – 8th Edition 13.16 Silberschatz, Galvin and Gagne ©2009
  17. A Kernel I/O Structure Operating System Concepts – 8th Edition 13.17 Silberschatz, Galvin and Gagne ©2009
  18. Characteristics of I/O Devices Operating System Concepts – 8th Edition 13.18 Silberschatz, Galvin and Gagne ©2009
  19. Characteristics of I/O Devices (Cont.) s Subtleties of devices handled by device drivers s Broadly I/O devices can be grouped by the OS into q Block I/O q Character I/O (Stream) q Memory-mapped file access q Network sockets s For direct manipulation of I/O device specific characteristics, usually an escape / back door q Unix ioctl() call to send arbitrary bits to a device control register and data to device data register Operating System Concepts – 8th Edition 13.19 Silberschatz, Galvin and Gagne ©2009
  20. Block and Character Devices s Block devices include disk drives q Commands include read, write, seek q Raw I/O, direct I/O, or file-system access q Memory-mapped file access possible 4 File mapped to virtual memory and clusters brought via demand paging q DMA s Character devices include keyboards, mice, serial ports q Commands include get(), put() q Libraries layered on top allow line editing Operating System Concepts – 8th Edition 13.20 Silberschatz, Galvin and Gagne ©2009
ADSENSE

CÓ THỂ BẠN MUỐN DOWNLOAD

 

Đồng bộ tài khoản
2=>2