Bài giảng Thiết kế logic số (VLSI design): Chương 4.3 trình bày về quy trình thiết kế trên FPGA và một số nội dung như: VHDL and Schematic, Synthesis, Synthesis - netlist, Synthesis – Technology Schematic,... Mời các bạn cùng tham khảo.
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Nội dung Text: Bài giảng Thiết kế logic số (VLSI design): Chương 4.3 - Trịnh Quang Kiên
- Thiết kế logic số
(VLSI design)
Bộ môn KT Xung, số, VXL
06/2010
- Quy trình thiết kế trên FPGA
ISE (Intergrated Software Enviroment)
- Quy trình thiết kế trên FPGA
Design and implement a simple unit permitting to
Specification (Lab Experiments)
speed up encryption with RC5similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds…..
VHDL description (Your Source Files)
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RC5_core is
Functional simulation
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;
Synthesis
Post-synthesis simulation
- Quy trình thiết kế trên FPGA
Implementation
Timing simulation
Configuration
On chip testing
- VHDL and Schematic
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity compare_module is
Port (value : in std_logic_vector (3 downto 0);
res : out std_logic);
end compare_module;
architecture Behavioral of compare_module is
signal std : std_logic_vector (4 downto 0);
begin
val
- Synthesis
- Synthesis
UNISIM Library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity compare_module is
Port (value : in std_logic_vector (3 downto 0);
res : out std_logic);
end compare_module;
architecture Behavioral of compare_module is
signal std : std_logic_vector (4 downto 0);
begin
val
- Synthesis netlist
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity sp3_led is
port (
LED1 : out STD_LOGIC;
LED2 : out STD_LOGIC;
...
);
end sp3_led;
architecture Structure of sp3_led is
signal SW8_IBUF_31 : STD_LOGIC;
begin
LED81 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => SW8_IBUF_31,
I1 => SW7_IBUF_29,
O => LED8_OBUF_15
);
...
- Synthesis – Technology Schematic
- Synthesis – RTL Schematic
- Synthesis – UCF file
# IO location defination
NET "HIGH_voltage" LOC = P102;
NET "LOW_voltage" LOC = P100;
NET "voltage[0]" LOC = P160;
NET "voltage[1]" LOC = P161;
NET "voltage[2]" LOC = P162;
NET "voltage[3]" LOC = P163;
# Timing constraint
INST "LOW_voltage" TNM = "OUT_REG";
INST "HIGH_voltage" TNM = "OUT_REG";
NET "voltage[0]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP
"OUT_REG" RISING;
NET "voltage[1]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP
"OUT_REG" RISING;
NET "voltage[2]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP
"OUT_REG" RISING;
NET "voltage[3]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP
"OUT_REG" RISING;
- Implementation
- Translate
Synthesis
Circuit netlist Timing Constraints
Constraint Editor
Electronic Design Native
Interchange Format Constraint
File
EDIF NCF UCF User Constraint File
Translation
NGD Native Generic Database file
- Mapping
- Chương III FPGA
Place & Route
- FPGA Verification
- Giao thức truyền tin nối tiếp
IDLE START DATA PARITY STOP IDLE
RX
Tbraud
Bit counter x 0 0 1 2 3 4 5 6 7 8 0
SAMPLE
ONE BIT
RECEIVING
RX
Sample counter 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
- Máy trạng thái khối UART
IDLE
CNT16 = 8 and RX = 1
CNT_BIT = 8
RX = 0, Rx_Reg = 1
START FRAME
RECEIVE DETECTOR
DATA
CNT16 = 8 and RX = 0
- Sơ đồ khối UART
SAMPLE COUNTER BIT COUNTER
CLK
CLOCK DIVIDER CLK16
CNT CNT
RESET RESET
ENABLE ENABLE
nRESET
FSM (FINITE STATE MACHINE)
RX_REG RX_REG
Rx
RECEIVE_REG SHIFT_ENABLE
LOAD
DATA REG
LEDs
- Khối giao tiếp VGA
Thêm vào BST
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