Bài giảng VHDL_Hardware Description Language

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VHDL là ngôn ngữ mô tả phần cứng cho các mạch tích hợp tốc độ rất cao, là một loại ngôn ngữ mô tra phần cứng được phát triển dùng cho chương trình VHSIC của bộ quốc phòng Mỹ, trước khi VHDL ra đời thì đã có khá nhiều ngôn ngữ mô tả phần cứng nhưng các ngôn ngữ đó không có nhiều tính năng ưu việt như ngôn ngữ VDH, tài liệu này sẽ cung cấp cho các bạn nhiều thông tin hữu ích về ngôn ngữ VHDL...

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Nội dung Text: Bài giảng VHDL_Hardware Description Language

Hardware Description Language á 1.1. ] á ] _ è ] _ ] ] á• 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 1 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 2 Hardware Description Language Hardware Description Language ] ò ] ] ] ] ]] ] ] ] ] ] - ] ] ] - ] ] ] _í ] -1987 ]] ] _] ] _] ] -è ] ] ] ] ] ] ] ] -] ] ] ] _ ] ]] - ] ] -] ] ] 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 3 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 4 Hardware Description Language Hardware Description Language
ò ò è ] ]é] ] ] ] - ] ] ] ]_ ] - ]] ]_ ] ] ] ]]_ ] ] é ] - ] ] ] - ] ] ] ]] ] - _ ]é ] ] ] ]] _ _ ] ] ] ]_ - ] ] ] _ IC- ] ] ] Specified). 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 5 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 6 Hardware Description Language Hardware Description Language ò á ] é _ - ] ] ] ] ]] ]] ] 1.2. ] _ ] ]é] ]_ _] é ]_ ]_ ] ] - ] ] ]_ ]] ] ] ] ] ]é ] ] ] ] ] ]] ] 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 7 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 8 Hardware Description Language Hardware Description Language
á ] _ (Register Transfer Level) ] ] _ ]_ ] - ] ]] ] ] - ] ] ] _ ] ] ] ] ] ] 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 9 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 10 Hardware Description Language Hardware Description Language ] _ á ] ] _ ]_ á ] ] http://www.xilinx.com/support/download/index.htm http://www.xilinx.com/webpack/index.htm . 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 11 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 12 Hardware Description Language Hardware Description Language
] Hardware Description Language ] á ê è ] á• ] 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 13 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 14 Hardware Description Language Hardware Description Language á ê è úè á á - á _ ò è é èé - ò _ è é - LIBRARY: - í é á• é é - á é _ - á 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 15 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 16 Hardware Description Language Hardware Description Language
á ê úè á _ ò _ 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 17 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 18 Hardware Description Language Hardware Description Language ] ] ] ] - ] std work ] ] ]_] khai ] ] ] ] ieee ] ra. LIBRARY library_name; - ] IEEE khi _ STD_LOGIC, USE library_name.package_name.package_parts; STD_ULOGIC . ] ] à std_logic_1164 ] LIBRARY ieee; USE ieee.std_logic_1164.all std_logic_arith ] _ ] ] ] ]] ] LIBRARY std; ]] _ ] ]] _ _] USE std.standard.all; - std_logic_signed ] ] ] ] ] ] ]_] _ LIBRARY work; - std_logic_unsigned ] ] ]] USE work.all; ]] ]_] _ 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 19 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 20 Hardware Description Language Hardware Description Language
á ê ò _ ] úè ENTITY entity_name IS PORT ( á _ port_name : signal_mode signal_type; port_name : signal_mode signal_type; ò _ ...); END entity_name; - Singnal Mode: IN, OUT, INOUT, BUFFER. - - Entity_name: í Y ê . 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 21 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 22 Hardware Description Language Hardware Description Language á ê ê úè ENTITY nand_gate IS á _ PORT (a, b : IN BIT; x : OUT BIT); ó ò _ END nand_gate; é _ ) 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 23 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 24 Hardware Description Language Hardware Description Language
á ê ] ] ] _ ] _ úè ] á _ ARCHITECTURE architecture_name OF entity_name IS [-- _] ] BEGIN BEGIN ò _ (code) END architecture_name; ARCHITECTURE my_arch OF nand_gate IS BEGIN x
] _] VD2: ENTITY example IS PORT ( a, b, clk: IN STD_LOGIC; q: OUT STD_LOGIC); END example; --------------------------------------- ARCHITECTURE example OF example IS SIGNAL temp : STD_LOGIC; BEGIN temp
á à á à â standard std: è ] ]ê _ BIT, BOOLEAN, INTEGER REAL. - _ ] - Scalar. std_logic_1164 ieee: è ] ]_ ê - ] _ ] STD_LOGIC STD_ULOGIC. _ ] std_logic_arith ieee: è ] ] SIGNED ê UNSIGNED, - _ _ _ ] ] ] ] : conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), conv_std_logic_vector(p, b). - ] _ ] ] ]ê _ ] std_logic_signed std_logic_unsigned ieee: ] ] cho ] ] STD_LOGIC_VECTOR ]] - khi _ SIGNED ] é UNSIGNED. - ] 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 33 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 34 Hardware Description Language Hardware Description Language ò ò SIGNAL x: BIT;-- ú _ ê_ ] SIGNAL y: BIT_VECTOR (3 DOWNTO 0); ] -- ô à ú _] ] ] SIGNAL SIGNAL w: BIT_VECTOR (0 TO 7); -- á à ú _] _ _ ú ê ìé _ ú ù _] ] ] -_] 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 35 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 36 Hardware Description Language Hardware Description Language
STD_ULOGIC( STD_ULOGIC_VECTOR) SIGNAL x: STD_LOGIC; ] ] -- _ ] ] _ ] ] ] _ SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001"; -- _ ] ] - -- _] -- ] _] 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 37 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 38 Hardware Description Language Hardware Description Language á à â á à â BOOLEAN: True/False ] ] ] ] ] - VD1: type time is range imlementation_defined; units; fs; Ps = 1000fs; _] ns = 1000ps; us = 1000ns; ms = 1000us; ] _] - Sec= 1000ms; Min= 60sec; Hr = 60min; End units; 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 39 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 40 Hardware Description Language Hardware Description Language
á à â á à â ] ] ] ] _ ] ] ] ] _ ] ] _ ]] ê std_logic_arith ] ieee. ] ] ]] ] VD2: type resistance is range 0 to 1E8; STD_LOGIC_VECTOR, V= = L L units; ohms; N A A kohms = 1000 ohms; INTEGER Mohms = 1E6 ohms; End units; 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 41 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 42 Hardware Description Language Hardware Description Language ô _ ô ì x0
á à ì SIGNAL a: BIT; SIGNAL b: BIT_VECTOR(7 DOWNTO 0); á à â SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0); á à â SIGNAL e: INTEGER RANGE 0 TO 255; á à _ ... a
á â ò TYPE color IS (red, green, blue, white); ]] ê -- __ ] TYPE integer IS RANGE -2147483647 TO +2147483647; ] _ _ ]] ] ù ê_ _ ê â TYPE my_integer IS RANGE -32 TO 32; ãâ _ ú -- ] ]ê â_ ú TYPE student_grade IS RANGE 0 TO 100; -- ] ] ] ]ê éé _ _ 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 49 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 50 Hardware Description Language Hardware Description Language á à á à _ ò á à â á à â ê_ _ ê_ _ è_ á à _ _ ù ê_ á à _ ê_ ì ê _ _ô ê_ _ _ á à ú íú á à ú ê_ ê_ á é á à ô ì 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 51 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 52 Hardware Description Language Hardware Description Language
á à _ á à _ ì ì ] ] _] ] SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH; _ _ -- _ SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1'; SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z'; SIGNAL a: BIT; -- -'). SIGNAL b: STD_LOGIC; -- SIGNAL c: my_logic; SUBTYPE my_color IS color RANGE red TO blue; ... -- _] ] ] b
á à ì (Arrays ) ] ]] _] ] ] ]ê ] _] ] ] ] ] TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array è ] _ ] ]] ê TYPE matrix IS ARRAY (0 TO 3) OF row; -- 1Dx1D array ] ]é SIGNAL x: matrix; -- 1Dx1D signal ] _] _ ] è] ] _ ]_] ] TYPE type_name IS ARRAY (specification( )) OF data_type; è _ TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL signal_name: type_name [:= initial_value]; ] ] _] ] ] ] _] ] 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 57 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 58 Hardware Description Language Hardware Description Language ì ì ] á sau hai è. _ _ - _] SIGNAL ] VARIABLE ]. vector, í ú ô. - ] _] _] ] ] ] ] ] ] TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; -- 2D array ... :="0001"; -- for 1D array ... :=('0','0','0','1') -- for 1D array ... :=(('0','1','1','1'), ('1','1','1','0')); -- for 1Dx1D or-- 2D array 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 59 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 60 Hardware Description Language Hardware Description Language
ì óì ì óì ] ] x(0)
á à á à á à â á á ô ê ú ê_ _ _ á à â á à _ ì: á à á à TYPE birthday IS RECORD á à day: INTEGER RANGE 1 TO 31; á é á à month: month_name; END RECORD; ì 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 65 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 66 Hardware Description Language Hardware Description Language á à á à è ô ê_ _ ú ì è _ ] std_logic_arith ] ieee ] ] ] qua sau) _] ] ] ] _ SIGNAL x: SIGNED (7 DOWNTO 0); ] ] ] ] ]ê SIGNAL y: UNSIGNED (0 TO 3); ] ] ] ] ] _] ]_] ] ]_] ] ! _ ô - _] ]] 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 67 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 68 Hardware Description Language Hardware Description Language
á à á à ì ì( ú ú ô ) ] ] _ ] ] _ LIBRARY ieee; signed/unsigned: USE ieee.std_logic_1164.all; -- _] ] ] LIBRARY ieee; ... USE ieee.std_logic_1164.all; SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0); USE ieee.std_logic_arith.all; -- ] ] SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0); ... SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL a: IN SIGNED (7 DOWNTO 0); ... SIGNAL b: IN SIGNED (7 DOWNTO 0); v
á é á à á é á à Conv_integer(p): Y ô à á - ] tham p _ INTEGER, UNSIGNED, ] ] ] SIGNED, ] STD_ULOGIC ] ] INTEGER. _ __ ] STD_LOGIC_VECTOR _] _ . ] ] _] ] Conv_unsigned(p, b): TYPE long IS INTEGER RANGE -100 TO 100; TYPE short IS INTEGER RANGE -10 TO 10; SIGNAL x : short; - ] tham p _ INTEGER, UNSIGNED, SIGNED, SIGNAL y : long; ] STD_ULOGIC ] ] UNSIGNED _] b bit. ... y
á à ì á à â TYPE byte IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array á à â TYPE mem1 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; -- 2D array TYPE mem2 IS ARRAY (0 TO 3) OF byte; -- 1Dx1D array á à _ TYPE mem3 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(0 TO 7); -- 1Dx1D array á à SIGNAL a: STD_LOGIC; -- scalar signal SIGNAL b: BIT; -- scalar signal á à SIGNAL x: byte; -- 1D signal SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); -- 1D signal á à SIGNAL v: BIT_VECTOR (3 DOWNTO 0); -- 1D signal á é á à SIGNAL z: STD_LOGIC_VECTOR (x'HIGH DOWNTO 0); -- 1D signal SIGNAL w1: mem1; -- 2D signal ì SIGNAL w2: mem2; -- 1Dx1D signal SIGNAL w3: mem3; -- 1Dx1D signal 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 77 1/9/2012 8:05:21 PM Very High Speed Intergated Circuit 78 Hardware Description Language Hardware Description Language ì ì _ í à _ í à x