Chapter3: Modules and Hierarchical structure

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The Verilog HDL supports a hierarchical hardware description structure by allowing modules to be embedded within other modules. Higher level modules create instances of lower level modules and communicate with them through input, output, and bidirectional ports. These module input/output (I/O) ports can be scalar or vector.

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Nội dung Text: Chapter3: Modules and Hierarchical structure

NATIONAL UNIVERSITY OF HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING LECTURE VERILOG Subject: Hardware Description Language Chapter3: Modules and Hierarchical structure Lecturer: Lam Duc Khai 1
Agenda 1. Chapter 1: Introduction ( Week1) 2. Chapter 2: Fundamental concepts (Week1) 3. Chapter 3: Modules and hierarchical structure (Week2) 4. Chapter 4: Primitive Gates – Switches – User defined primitives (Week2) 5. Chapter 5: Structural model (Week3) 6. Chapter 6: Behavioral model – Combination circuit (Week4) 7. Chapter 7: Behavioral model – Sequential circuit (Week5) 8. Chapter 8: Tasks and Functions (Week6) 9. Chapter 9: State machines (Week6) 10. Chaper 10: Testbench and verification (Week7) 2
Agenda 3. Chapter 3: Module and Hierarchical structure Hierarchical structure Modules Instances 3
Hierarchical structure • The Verilog HDL supports a hierarchical hardware description structure by allowing modules to be embedded within other modules. Higher level modules create instances of lower level modules and communicate with them through input, output, and bidirectional ports. These module input/output (I/O) ports can be scalar or vector. 4
Hierarchical structure (Cont’d) Top-down design methodology Top-level block identify enough to build Cannot further be divided 5
Hierarchical structure (Cont’d) Bottom-up design methodology Top-level block, the final block in design build Building blocks that are available is identified 6
Hierarchical structure (Cont’d) Design Methodologies • A combination of top-down and bottom-up flows is typically used – Design architects define the specifications of the top-level block – Logic designers break up the functionality into blocks and sub-blocks. – At the same time, circuit designers are designing optimized circuits for leaf-level cells. They build higher-level cells by using these leaf cells. – The flow meets at an intermediate point 7
Hierarchical structure (Cont’d) Example: 4-bit Ripple Carry Counter Ripple Carry Counter T-flipflop 8 Design Hierarchy
Modules • A module is the basic building block in Verilog – Can be an element or a collection of lower-level design blocks – Provide functionality for higher-level block through its port interface – Hide internal implementation – Is used at many places in the design – Allows designers modify module internals without effecting the rest of design 9
Modules (Cont’d) Typical Module Components Diagram Module name, Port list (optional, if there are ports) Port declarations Parameter list Declaration of variables (wires, reg, integer etc.) Instantiation of inner (lower-level) modules Structural statements (i.e., assign and gates) Procedural blocks (i.e., always and initial blocks) Tasks and functions endmodule declaration 10
Modules (Cont’d) Example: 4-bit Ripple Carry Counter Ripple Carry Counter Module T-flipflop Module Module 11 Design Hierarchy
Modules (Cont’d) Module description module module name ( port name, port name,…); module_port declaration module data type declaration logic description part A part of a chip, or whole the chip endmodule A module definition The file name for RTL source must be “module name.v” 12
Modules (Cont’d) Module_port declaration module module name ( port name, port name,…); Declare whether the ports are input and/or output module_port declaration input port name, port name, …; output port name, port name, …; inout port name, port name, …; module module data_conv ( a, b, …); 4 4 a input [3:0] a; e 8 A part of a chip, 4 b input [7:0] b; f or whole the 1 16 c output [3:0] e, f; g chip 1 d output [15:0] g; inout c, d; 13 ports
Modules (Cont’d) Outside connectors Port Rules Diagram to internal ports, i.e., variables corresponding to ports in instantiation EXTERNAL of internal module MODULE wire Example: module external wire inout reg a; wire b; internal in(a, b); //instantiation Internal ports port-connector … endmodule input output wire reg or wire wire module internal(x, y) INTERNAL reg or wire input x; MODULE output y; wire x; reg y; … endmodule General rule (with few exceptions) Ports in all modules except for the stimulus module should be wire. Stimulus module has registers to set data for internal modules and wire ports only to read data from internal modules. 14
Modules (Cont’d) Data type declaration module module name ( port name, port name,…); module_port declaration Data type declaration Declare characteristics of variables for net data type wire variable name, variable name, …; wire variable name, variable name, …; module wire [3:0] a; 4 q1 4 a wire [7:0] b; q3 e 8 SEL 4 f b wire c, d; 1 16 c wire [3:0] f; g 1 q2 sel3 d wire [7:0] q1, q2, q3, q4; wire sel3, …; …. 15
Modules (Cont’d) Data type declaration (Cont’d) module module name ( port name, port name,…); Define signals which are output of FF, registers, and module_port declaration other memory elements as register type variable. Data type declaration for register data type reg variable name, variable name, …; reg variable name, variable name, …; module 4 4 wire [3:0] e; a e q2 8 4 b wire [15:0] g; f 1 16 c wire q2; g 1 d …. Note: Output does not have to be declared as register data type Input (inout) must not be declared as register data type 16
Modules (Cont’d) Example: Mistakes and correct on register and net data type module1 module2 reg reg wire wire reg wire wire wire reg module2_1 reg reg reg wire wire reg wire wire reg The output of memory element They must be defined as wire at must be defined as reg these points. : memory element 17
Modules (Cont’d) Example: Mistakes and correct on register and net data type (Cont’d) module1 module2 reg reg wire wire reg reg reg reg wire reg wire module2_1 reg wire wire wire wire reg reg reg wire wire wire wire Assume gates are not defined by using reg always nor function statements wire wire wire Suppose this part is programmed by wire using always statement. 18
Modules (Cont’d) Example: Mistakes and correct on register and net data type (Cont’d) Note: reg data type cannot be declared as an input !!! module1 module2 wire wire wire wire reg reg wire wire reg reg reg reg wire reg wire module2_1 wire reg wire reg wire wire wire wire wire reg reg reg reg wire wire wire wire Explain later reg reg wire wire reg wire Suppose this part is programmed by wire using always statement. 19
Modules (Cont’d) Logic description part (Cont’d) module module name ( port name, port name,…); module_port declaration Data type declaration The main part of logic is Logic description part written here. module endmodule 4 4 a e 8 4 b f 1 16 c g 1 d Logic is coded in this part using various operator including connections to lower level blocks. 20