Thiết kế và thực hiện hệ thống VLSI - 02

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In equilibrium, the drift and diffusion components of current are balanced; therefore the net current flowing across the junction is zero.

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Nội dung Text: Thiết kế và thực hiện hệ thống VLSI - 02

Design and Implementation of VLSI Systems Lecture 02 Thuan Nguyen Faculty of Electronics and Telecommunications, University of Science, VNU HCMUS Spring 2011 1
LECTURE 2: CMOS CIRCUIT MOS Transistor 1 CMOS Logic 2 2
LECTURE 2: CMOS CIRCUIT MOS Transistor 1 CMOS Logic 2 3
MOS TRANSISTOR silicon IMPACT OF DOPING ON 4.9951022 atoms in cm3 Resistivity 3.2  105 Ωcm SILICON RESISTIVITY dope with dope with phosphorous boron  or arsenic  p-type n-type 1 atom in billion  88.6 Ωcm 1 atom in billion  266.14 Ωcm 1 atom in million  0.114 Ωcm 1 atom in million  0.344 Ωcm 1 atom in thousand  0.00174 Ωcm 1 atom in thousand  0.00233 Ωcm 4  Electrons are more mobile/faster than holes
WHAT HAPPENS & N TYPES? IF WE SANDWICH P A Al p n B One-dimensional representation  In equilibrium, the drift and diffusion components of current are balanced; therefore the net current flowing across the 5 junction is zero.
WHAT HAPPENS & N TYPES? IF WE SANDWICH P 6
PN-JUNCTION REGIONS OF OPERATION A forward bias decreases the potential In reverse bias, the width drop across the of the depletion region junction. As a result, increases. The diode acts the magnitude of the as voltage-controlled electric field decreases capacitor. and the width of the depletion region 7 narrows.
NMOS AND PMOS TRANSISTORS Each transistor consists of a stack of a conducting gate, an insulating layer of silicon dioxide and a semiconductor substrate (body or bulk) nMOS transistor pMOS transistor 8 Body is typically grounded Body is typically at supply voltage
NMOS TRANSISTOR Source Gate Drain Polysilicon SiO2 n+ n+ p bulk Si g=0: When the gate is at a low voltage (VGS < VTN):  p-type body is at low voltage  source and drain-junctions diodes are OFF  transistor is OFF, no current flows g=1: When the gate is at a high voltage (VGS ≥ VTN):  negative charge attracted to body  inverts a channel under gate to n-type  transistor ON, current flows, transistor can be viewed as a resistor 9
NMOS PASS ‘0’ MORE STRONGLY ‘1’ THAN Source Gate Drain Polysilicon SiO2 n+ n+ p bulk Si • Why does ‘1’ pass degraded? 10
PMOS TRANSISTOR Source Gate Drain Polysilicon SiO2 p+ p+ n bulk Si g=0: When the gate is at a low voltage (VGS < VTP):  positive charge attracted to body  inverts a channel under gate to p-type  transistor ON, current flows g=1: When the gate is at a high voltage (VGS ≥ VTP):  negative charge attracted to body  source and drain junctions are OFF  transistor OFF, no current flows 11
PMOS PASS ‘1’ MORE STRONGLY THAN ‘0’ Source Gate Drain Polysilicon SiO2 p+ p+ n bulk Si • Why does ‘0’ pass degraded? 12
LECTURE 2: CMOS CIRCUIT MOS Transistor 1 CMOS Logic 2 13
CMOS LOGIC VDD A Y A Y GND pMOS + nMOS = CMOS An nMOS and pMOS make up an inverter 14
MORE CMOS GATES Y What is this gate function? A B 15
3-INPUT NANDS pMOS pull-up network inputs output nMOS pull-down network What are the advantages of CMOS circuit style? 16
SERIES-PARALLEL COMBINATIONS nMOS: 1 = ON  a a a a a 0 0 1 1 g1 pMOS: 0 = ON  g2 0 1 0 1 b b b b b Series: both must be ON  (a) OFF OFF OFF ON Parallel: either can be ON  a a a a a 0 0 1 1 g1 g2 0 1 0 1 b b b b b (b) ON OFF OFF OFF a a a a a g1 g2 0 0 0 1 1 0 1 1 b b b b b (c) OFF ON ON ON a a a a a g1 g2 0 0 0 1 1 0 1 1 17 b b b b b (d) ON ON ON OFF
WHAT ARE THE TRANSISTOR SCHEMATICS OF THE NOR GATE? A B Y 1:59 2:00 0:58 E:57 :01 :02 :03 :04 :05 :06 :07 :08 :09 :10 :12 :13 :14 :15 :16 :17 :18 :19 :20 :21 :22 :23 :24 :25 :26 :27 :28 :29 :30 :31 :32 :33 :34 :35 :36 :37 :38 :39 :40 :41 :42 :43 :44 :45 :46 :47 :48 :49 :50 :51 :52 :53 :54 :55 :56 :11 nd 18
SUMMARY Source Gate Drain Source Gate Drain Polysilicon Polysilicon SiO2 pMOS SiO2 nMOS p+ p+ n+ n+ n p bulk Si bulk Si 19 pMOS strong ‘1’, weak ‘0’  VDD nMOS strong ‘0’, weak ‘1’  VSS
SUMMARY  NOT: pMOS + pull up nMOS + pull down  NAND2: pMOS + parallel + pull up nMOS + serial + pull down  NOR2: pMOS + serial + pull up nMOS + parallel + pull down 20