Verilog to C compiler: Simulator generator

Certified that the work contained in the thesis entiled " Verilog-to-C-Compiler: Simulator Generator " by " Anand Vivek Srivastava", has been carried out under my supervision and that this work has not been submitted elsewhere for a degree. This paper describes a compiler, which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics, of Verilog and performs logic minimization. Busses of up to 32 or 64 bits can be modeled as C integers...