Gate level modeling

Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation .Pass Transistors We have assumed source is grounded What if source 0? VDD – e.g. pass transistor passing VDD VDD Vg = VDD – If Vs VDD-Vt, Vgs Vout = VDD – When Vin = VDD - Vout = 0 VDD – In between, Vout depends on Idsp transistor size and current Vin Vout – By KCL, must settle such that Idsn Idsn = |Idsp| – We could solve equations – But graphical solution gives more insight...

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Dataflow model For complex design: number of gates is very large - need a more effective way to describe circuit Dataflow model: Level of abstraction is higher than gate-level, describe the design using expressions instead of primitive gates Circuit is designed in terms of dataflow between register, how a design processes data rather than instantiation of individual gates RTL (register transfer level): is a combination of dataflow and behavioral modeling

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[ Team LiB ] 11.2 Examples In this section, we discuss how to build practical digital circuits, using switch-level constructs. 11.2.1 CMOS Nor Gate Though Verilog has a nor gate primitive, let us design our own nor gate,using CMOS switches.

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[ Team LiB ] 5.2 Gate Delays Until now, we described circuits without any delays (i.e., zero delay). In real circuits, logic gates have delays associated with them. Gate delays allow the Verilog user to specify delays through the logic circuits.

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[ Team LiB ] 5.1 Gate Types A logic circuit can be designed by use of logic gates. Verilog supports basic logic gates as predefined primitives. These primitives are instantiated like modules except that they are predefined in Verilog and do not need a module definition.

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[ Team LiB ] 6.1 Continuous Assignments A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net. This assignment replaces gates in the description of the circuit and describes the circuit at a higher level of abstraction.

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