Verilog programming

.Course Description • Provide students general and detail knowledge about how to build a CMOS chip • Learn and practice the Verilog (or VHDL) language for hardware programming

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This paper describes a compiler, which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics, of Verilog and performs logic minimization. Busses of up to 32 or 64 bits can be modeled as C integers whereas larger busses are automatically split. We describe the motivation, method and quality of the results.

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Max+Plus II cho phép chúng ta soạn thảo project với hai dạng sau: - Dạng text (chương trình có dạng văn bảng được thiết kế bằng ngôn ngữ VHDL, AHDL, Verilog). - Dạng Graphic (mạch điện). 1. Soạn thảo một project dạng Text Sau khi cài phần mềm Max+Plus II và setup licence xong, ta khởi động Max+Plus II bằng cách nhấp vào biểu tượng Max+Plus II. Hay vào start=program=Max+plus II 10.2 Baseline= Max+plus II 10.2 Baseline. Khi đó màn hình sẽ xuất hiện cửa sổ: Nhấp vào option để khai báo đường dẫn licence: Nhấp chọn license setup và chọn đường...

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Procedural continuous assignments can be used to override the assignments on registers and nets. assign and deassign can override assignments on registers. force

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Time Scales Often, in a single simulation, delay values in one module need to be defined by using certain time unit, e.g., 1 µs, and delay values

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Overriding Parameters Parameters can be defined in a module definition, as was discussed earlier in Section 3.2.8, Parameters. However, during compilation

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Tasks and functions are used to define common Verilog functionality that is used at many places in the design.

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Examples In order to illustrate the use of behavioral constructs discussed earlier in this chapter, we consider three examples in this section. The first two, 4-to-1 multiplexer and 4-bit counter, are taken from Section

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Generate Blocks Generate statements allow Verilog code to be generated dynamically at elaboration time before the simulation begins. This facilitates the creation of parametrized models.

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Sequential and Parallel Blocks Block statements are used to group multiple statements to act together as one. In previous examples, we used keywords begin and end to group multiple statements.

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Loops There are four types of looping statements in Verilog: while, for, repeat, and forever. The syntax of these loops is very similar to the syntax of loops in the C programming language.

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Conditional Statements Conditional statements are used for making decisions based upon certain conditions.

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Timing Controls Various behavioral timing control constructs are available in Verilog. In Verilog, if there are no timing control statements

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Procedural Assignments Procedural assignments update values of reg, integer, real, or time variables.

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Continuous assignment is one of the main constructs used in dataflow modeling. A continuous assignment is always active and the assignment expression is evaluated

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Examples A design can be represented in terms of gates, data flow, or a behavioral description. In this section, we consider the 4-to-1 multiplexer

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Expressions, Operators, and Operands Dataflow modeling describes the design in terms of expressions instead of primitive gates. Expressions, operators

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Exercises 1: Create your own 2-input Verilog gates called my-or, my-and and my-not from 2-input nand gates. Check the functionality of these gates with a stimulus module.

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A behavioral description expresses a digital circuit in terms of the algorithms it implements. A behavioral description does not necessarily include the hardware implementation details. Behavioral modeling

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8.1 Differences between Tasks and Functions Tasks and functions serve different purposes in Verilog. We discuss tasks and functions in greater detail in the following sections. However, first it is important to understand differences between tasks and functions, as outlined in Table 8-1. Table 8-1. Tasks and Functions Functions A function can enable another function but not another task. Functions always execute in 0 simulation time. Functions must not contain any delay, event, or timing control statements. Functions must have at least one input argument. They can have more than one input.

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